{
 "company": "cadence-design-systems",
 "as_of": "2026-10-08",
 "choices": [
  {
   "id": "cadence-design-systems-p01",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Core priorities",
   "statement": "Tan prioritized analog and mixed-signal design plus verification and debugging.",
   "event_date": "2009",
   "date_precision": "year",
   "evidence_kind": "participant_account",
   "sources": [
    "CD1"
   ]
  },
  {
   "id": "cadence-design-systems-p02",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Interoperability",
   "statement": "Cadence supported tools working with other suppliers\u2019 products.",
   "event_date": "2009",
   "date_precision": "year",
   "evidence_kind": "participant_account",
   "sources": [
    "CD1"
   ]
  },
  {
   "id": "cadence-design-systems-g01",
   "business": "Electronic design automation and semiconductor IP",
   "category": "go_to_market",
   "dimension": "Customer engagement",
   "statement": "Tan called for earlier and closer work with chip customers, foundries and IP providers.",
   "event_date": "2009",
   "date_precision": "year",
   "evidence_kind": "participant_account",
   "sources": [
    "CD1"
   ]
  },
  {
   "id": "cadence-design-systems-p03",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Custom design",
   "statement": "Virtuoso supported analog, custom and mixed-signal design and simulation.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-p04",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Digital implementation",
   "statement": "Innovus supported physical implementation and signoff for digital chips.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-p05",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Simulation",
   "statement": "Xcelium provided logic simulation.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-p06",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Formal verification",
   "statement": "Jasper supplied formal verification.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-p07",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Hardware emulation",
   "statement": "Palladium accelerated large functional verification workloads.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-p08",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Prototyping",
   "statement": "Protium supported FPGA-based prototypes and earlier software development.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-p09",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Reusable IP",
   "statement": "Cadence licensed interface and subsystem IP for incorporation into customer designs.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-p10",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Manufacturing alignment",
   "statement": "Foundry process design kits connected design tools with manufacturing signoff requirements.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-p11",
   "business": "Electronic design automation and semiconductor IP",
   "category": "product",
   "dimension": "Board and system work",
   "statement": "Allegro and OrCAD addressed board and packaging design.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-g02",
   "business": "Electronic design automation and semiconductor IP",
   "category": "go_to_market",
   "dimension": "Technical sales",
   "statement": "Applications engineers provided pre-sales and post-sales support.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-g03",
   "business": "Electronic design automation and semiconductor IP",
   "category": "go_to_market",
   "dimension": "Evaluation",
   "statement": "Sales activity included demonstrations and on-site customer evaluations; cycles could run six months or longer.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-g04",
   "business": "Electronic design automation and semiconductor IP",
   "category": "go_to_market",
   "dimension": "Term access",
   "statement": "Software licenses generally ran two to three years with updates.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-g05",
   "business": "Electronic design automation and semiconductor IP",
   "category": "go_to_market",
   "dimension": "Product mix",
   "statement": "Some time-based contracts allowed customers to remix the licensed products.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-g06",
   "business": "Electronic design automation and semiconductor IP",
   "category": "go_to_market",
   "dimension": "Indirect coverage",
   "statement": "Resellers primarily marketed OrCAD and some Allegro products.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-g07",
   "business": "Electronic design automation and semiconductor IP",
   "category": "go_to_market",
   "dimension": "Hardware commercial model",
   "statement": "Emulation hardware could be sold, leased or accessed through a managed cloud arrangement.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  },
  {
   "id": "cadence-design-systems-g08",
   "business": "Electronic design automation and semiconductor IP",
   "category": "go_to_market",
   "dimension": "IP economics",
   "statement": "Certain semiconductor IP agreements included royalties on customer shipments.",
   "event_date": "2025",
   "date_precision": "year",
   "evidence_kind": "company_described_offering",
   "sources": [
    "CD3"
   ]
  }
 ]
}